Generally, integrated circuits (ICs) comprise individual devices, such as transistors, capacitors, or the like, formed on a substrate. Front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are patterned in a wafer. Back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring or metal layers on the wafer. It includes interconnecting contacts, metal layers, and bonding sites for chip-to-package connections.
As technologies progress, ICs are characterized by decreasing dimension requirements over previous generation devices. However, such a decrease in dimensions is limited by the photolithography tools used in the fabrication of the devices. The minimum size of features and spaces fabricated by a photolithography tool is dependent upon the tool's resolution capabilities. Alternative methods may exist to provide for increased resolution capabilities and decreased minimum pitch (e.g., sum of the feature size and the width of a space between features); however, these methods may also fail to provide adequate critical dimensions. Additionally, the methods of reducing pattern size are often inefficient for example, adding costs and time to device fabrication.